1. Field of the Invention
This invention relates to improvements in an electrically reprogrammable nonvolatile memory device having a gate electrode structure of two or more layers.
2. Description of the Related Art
A Flash EEPROM consisting of a single transistor/ cell, which are replacing ultraviolet erasable EPROM, have been attracting attention these days in the field of nonvolatile semiconductor memory devices. FIG. 1 shows a cell transistor of the Flash EEPROM having a two-layer polycrystalline silicon gate structure. In a p-type silicon substrate 21, a source diffusion layer 22 and a drain diffusion layer 23 are formed. The depth of the source diffusion layer 22 is such that its junction break down voltage is sufficiently larger than a voltage applied to the source diffusion layer 22 during erasure operation. Formed on the p-type silicon substrate 21 between the source diffusion layer 22 and drain diffusion layer 23 is a gate oxide film 24, on which a floating gate electrode 25 is formed. On the floating gate electrode 25, an insulating film 26 is formed, on which a control gate 27 is formed.
Operation of the cell transistor of the Flash EEPROM will be explained hereinafter in FIG. 1. As with ultraviolet erasable EPROM, the writing of information is achieved by applying a high voltage to the control gate electrode 27 and drain diffusion layer 23, injecting hot electrons generated by the high electric field into the floating gate electrode 25, and storing therein to cause the transistor's threshold voltage value to increase. The information is erased by applying a high voltage (hereinafter, referred to as erasure voltage) to the source diffusion layer 22 and applying the GND potential on the control gate electrode 27. In this condition, an F.N tunneling current flows through the gate oxide film 24, extracting the stored electrons from the floating gate electrode 25 to the source diffusion layer 22.
The cell transistors of Flash EEPROM in FIG. 1 are generally constructed in array form and all the cell transistors in the array have the source diffusion layer 22 in common. This enables simultaneous erasure of the information stored in all cell transistors. In addition, the common source diffusion layer 22 makes the cell area almost the same as that for the ultraviolet erasable EPROM.
However, to set the erasure voltage at a practical value, e.g., 12.5 V, it is necessary to make the gate oxide film 24 as thin as approximately 100 .ANG.. This increases the probability that defects will develop in the gate oxide film 24, resulting in poorer production yields. The thinner gate oxide film causes gate-induced junction leakage current, together with the F.N tunneling current, to flow towards the substrate 21 and source diffusion layer 22. This prevents erasure of information from being performed adequately, thus interfering with the stable memory operation. Such drawbacks can be overcome by providing an internal charge pump circuit that has a very large power capacity. The size of the internal step-up circuit, however, becomes extremely large, making it impossible to obtain a practical chip size. An LSI external power supply could supply the erasure voltage (12.5 V), but this would conflict with the desire to simplify external power supplies to generate 5 V only.